At IEEE ISSCC 2026, imec introduces a 7-bit, 175GS/s wireline ADC implemented in 5nm FinFET technology, combining a record-small footprint (250 x 250µm²) and low conversion energy (2 . 2 pJ per sample) . The design builds on the massively time–interleaved slope–ADC architecture imec debuted in 2024, now enhanced with patented linearization and switched input buffer techniques to ensure precise signal conversion and wide bandwidth at ultra-high sampling rates . As data centers’ optical networks need constant upgrades to handle ever-higher throughputs and processing demands, wireline ADCs – essential in optical transceivers – often grow in size, requiring longer interconnects, and introducing parasitics and energy loss .